A 20 ns battery-operated 16 Mb CMOS DRAM
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Hiroyuki Yamauchi | Toshiaki Tsuji | Toru Iwata | Akihiro Sawada | Masanori Fukumoto | Michihiro Inoue | T. Suzuki | Masashi Agata | T. Taniguchi | Y. Odake | K. Sawada | T. Ohnishi | Tsutomu Fujita
[1] Hiroyuki Yamauchi,et al. A circuit design to suppress asymmetrical characteristics in high-density DRAM sense amplifiers , 1990 .
[2] Masaru Sasago,et al. A 64-Mb DRAM with meshed power line , 1991 .
[3] Richard C. Jaeger,et al. A high-speed sensing scheme for 1T dynamic RAMs utilizing the clamped bit-line sense amplifier , 1992 .
[4] Soo-In Cho,et al. Variable V/sub CC/ design techniques for battery-operated DRAMs , 1993 .