Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping
暂无分享,去创建一个
[1] Hsie-Chia Chang,et al. A 3.46 Gb/s (9141,8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).
[2] T. Wadayama,et al. Gradient descent bit flipping algorithms for decoding LDPC codes , 2008, ISITA 2008.
[3] Frank Kienle,et al. Low Complexity LDPC Code Decoders for Next Generation Standards , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.
[4] Tong Zhang,et al. On the Use of Soft-Decision Error-Correction Codes in nand Flash Memory , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.
[5] David Declercq,et al. Approaching maximum likelihood performance of LDPC codes by stochastic resonance in noisy iterative decoders , 2016, 2016 Information Theory and Applications Workshop (ITA).
[6] Seungjune Jeon,et al. Performance and Complexity of 32 k-bit Binary LDPC Codes for Magnetic Recording Channels , 2010, IEEE Transactions on Magnetics.
[7] A. K. Panda,et al. FPGA Implementation of 8, 16 and 32 Bit LFSR with Maximum Length Feedback Polynomial Using VHDL , 2012, 2012 International Conference on Communication Systems and Network Technologies.
[8] Thomas J. Richardson,et al. Error Floors of LDPC Codes , 2003 .
[9] David Declercq,et al. Efficient realization of probabilistic gradient descent bit flipping decoders , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).
[10] Marc P. C. Fossorier,et al. A modified weighted bit-flipping decoding of low-density Parity-check codes , 2004, IEEE Communications Letters.
[11] Ming Jiang,et al. An improvement on the modified weighted bit flipping decoding algorithm for LDPC codes , 2005, IEEE Communications Letters.
[12] David Declercq,et al. Channel Coding: Theory, Algorithms, and Applications Academic Press Library in Mobile and Wireless Communications , 2014 .
[13] Nenad Miladinovic,et al. Improved bit-flipping decoding of low-density parity-check codes , 2002, IEEE Transactions on Information Theory.
[14] Dariush Divsalar,et al. Short Protograph-Based LDPC Codes , 2007, MILCOM 2007 - IEEE Military Communications Conference.
[15] Bilgiday Yuce,et al. Fast and Efficient Circuit Topologies forFinding the Maximum of n k-Bit Numbers , 2014, IEEE Transactions on Computers.
[16] Martin Bossert,et al. A Modified Bit-Flipping Decoding Algorithm for Low-Density Parity-Check Codes , 2007, 2007 IEEE International Conference on Communications.
[17] Bane V. Vasic,et al. Fault-Tolerant Probabilistic Gradient-Descent Bit Flipping Decoder , 2014, IEEE Communications Letters.
[18] Khaled A. S. Abdel-Ghaffar,et al. Two reliability-based iterative majority-logic decoding algorithms for LDPC codes , 2009, IEEE Transactions on Communications.
[19] David Declercq,et al. Flexible, Cost-Efficient, High-Throughput Architecture for Layered LDPC Decoders with Fully-Parallel Processing Units , 2016, 2016 Euromicro Conference on Digital System Design (DSD).
[20] R. M. Tanner,et al. A Class of Group-Structured LDPC Codes , 2001 .
[21] Zhongfeng Wang,et al. Multi-Gb/s LDPC Code Design and Implementation , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.