Sequential Circuit Test Generation in a Genetic Algorithm Framework

Test generation using deterministic fault-oriented algorithms is highly complex and time-consuming. New approaches are needed to augment the existing techniques, both to reduce execution time and to improve fault coverage. In this work, we describe a genetic algorithm (GA) framework for sequential circuit test generation. The GA evolves candidate test vectors and sequences, using a fault simulator to compute the fitness of each candidate test. Various GA parameters are studied, including alphabet size, fitness function, generation gap, population size, and mutation rate, as well as selection and crossover schemes. High fault coverages were obtained for most of the ISCAS89 sequential benchmark circuits, and execution times were significantly lower than in a deterministic test generator in most cases.

[1]  L. Darrell Whitley,et al.  The GENITOR Algorithm and Selection Pressure: Why Rank-Based Allocation of Reproductive Trials is Best , 1989, ICGA.

[2]  James E. Baker,et al.  Reducing Bias and Inefficienry in the Selection Algorithm , 1987, ICGA.

[3]  Franc Brglez,et al.  Testability-Driven Random Test-Pattern Generation , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Kalyanmoy Deb,et al.  A Comparative Analysis of Selection Schemes Used in Genetic Algorithms , 1990, FOGA.

[5]  Lalit M. Patnaik,et al.  A Simulation-Based Test Generation Scheme Using Genetic Algorithms , 1993, The Sixth International Conference on VLSI Design.

[6]  Daniel G. Saab,et al.  CRIS: a test cultivation program for sequential VLSI circuits , 1992, ICCAD.

[7]  Janak H. Patel,et al.  PROOFS: a fast, memory-efficient sequential circuit fault simulator , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  David E. Goldberg,et al.  Genetic Algorithms in Search Optimization and Machine Learning , 1988 .

[9]  Eric Lindbloom,et al.  The Weighted Random Test-Pattern Generator , 1975, IEEE Transactions on Computers.

[10]  Thomas J. Snethen.  Simulator-oriented fault test generator , 1988, 25 years of DAC.

[11]  Melvin A. Breuer.  A Random and an Algorithmic Technique for Fault Detection Test Generation for Sequential Circuits , 1971, IEEE Transactions on Computers.

[12]  Elizabeth M. Rudnick,et al.  Application of simple genetic algorithms to sequential circuit test generation , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[13]  Thomas Michael Niermann,et al.  Techniques for sequential circuit automatic test generation , 1991 .

[14]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[15]  Sundaram Seshu,et al.  The Diagnosis of Asynchronous Sequential Switching Systems , 1962, IRE Trans. Electron. Comput..

[16]  Hans-Joachim Wunderlich.  Multiple distributions for biased random test patterns , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  D. E. Goldberg,et al.  Genetic Algorithms in Search , 1989 .

[18]  Kenneth A. De Jong,et al.  Generation Gaps Revisited , 1992, FOGA.

[19]  David E. Goldberg,et al.  Real-coded Genetic Algorithms, Virtual Alphabets, and Blocking , 1991, Complex Syst..

[20]  Prathima Agrawal,et al.  A directed search method for test generation using a concurrent simulator , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..