A Novel Channel Characteristics Estimation Methodology for High-Speed SerDes Interface on Flip-Chip Ball Grid Array Packages

This paper develops a systematic method to estimate the channel characteristics of a high-speed serializer/deserializer (SerDes) interface that is implemented on a build-up laminate flip-chip ball grid array (FCBGA) package. A microstrip multisize ring resonator method is developed to determine the extracted dielectric characteristics of a low-loss build-up substrate. The critical dimensions of the measurement structure of a high-speed SerDes interface are determined using scanning electron microscopy to estimate the channel characteristics. Finally, electromagnetic modeling is performed to systematically validate the measured mixed-mode S-parameters with the help of a double-sided probing system. The proposed systematic validation methodology is successfully validated by making the measurements of the high-speed SerDes interface up to 10 GHz.

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