Design and Optimization of Reliable Hardware Accelerators: Leveraging the Advantages of High-Level Synthesis

This work proposes an automatic method to generate opti- mized redundant hardware accelerator with maximum reliabil- ity given a single behavioral description for High-Level Syn- thesis (HLS). For this purpose, this work exploits one of the main advantages of C-based VLSI design over traditional RT- level design: The ability to generate micro-architectures with unique characteristics from the same behavioral description. This is typically done by setting different synthesis options to determine how to synthesize loops, arrays and functions and to specify the number and type of Functional Units (FUs) to be instantiated. The proposed method is composed of two main phases. The first phase performs HLS Design Space Exploration (DSE) leading to a trade-off curve of designs with a unique area, execution time and reliability. The second phase finds the most reliable system given an area and time constraint by either implementing time or space redundancy, or a mixture of both using any combinations of micro-architectures found by the explorer. This second phase has been formulated as an integer linear program (ILP). Experimental results show that the proposed method provides a 20% reliability increase compared to the most common approach of simply using a single micro-architecture and instantiating it multiple times with no significant area or timing overhead.

[1]  Joel Emer,et al.  A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[2]  Wayne Luk,et al.  Computer System Design: System-on-Chip , 2011 .

[3]  A. E. Eiben,et al.  Genetic algorithms with multi-parent recombination , 1994, PPSN.

[4]  Mahmut T. Kandemir,et al.  Reliability-centric high-level synthesis , 2005, Design, Automation and Test in Europe.

[5]  Lorenzo Alvisi,et al.  Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.

[6]  Benjamin Carrión Schäfer,et al.  On Time Redundancy of Fault Tolerant C-Based MPSoCs , 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

[7]  Benjamin Carrión Schäfer,et al.  S2CBench: Synthesizable SystemC Benchmark Suite for High-Level Synthesis , 2014, IEEE Embedded Systems Letters.

[8]  Martin Lukasiewycz,et al.  Reliability-Aware System Synthesis , 2007 .

[9]  Yuki Yoshikawa,et al.  High-level synthesis for multi-cycle transient fault tolerant datapaths , 2011, 2011 IEEE 17th International On-Line Testing Symposium.

[10]  Yun Liang,et al.  Design space exploration of multiple loops on FPGAs using high level synthesis , 2014, 2014 IEEE 32nd International Conference on Computer Design (ICCD).

[11]  Luca P. Carloni,et al.  On learning-based methods for design-space exploration with High-Level Synthesis , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[12]  Ramesh Karri,et al.  A Design Methodology For The High-level Synthesis Of Fault-tolerant Asics , 1992, Workshop on VLSI Signal Processing.