Un flot de conception pour applications de traitement du signal systématique implémentées sur FPGA à base d'Ingénierie Dirigée par les Modèles. (A Model Driven Engineering based design flow for systematic signal processing applications implemented on FPGA)

Dans cette these, nous proposons un flot de conception pour le developpement d'applications de traitement du signal systematique implementees sur FPGA. Nous utilisons une approche Ingenierie Dirigee par les Modeles (IDM) pour la mise en oeuvre de ce flot de conception, dont la specification des applications est decrite en UML. La premiere contribution de cette these reside dans la creation d'un metamodele isolant les concepts utilises au niveau RTL. Ces concepts sont extraits d'implementations materielles dediees de tâches a fort parallelisme de donnees. Par ailleurs, ce metamodele considere la technologie d'implementation FPGA et propose differents niveaux d'abstractions d'un meme FPGA. Ces multiples niveaux d'abstractions permettent un raffinement des implementations materielles. La seconde contribution est le developpement d'un flot de compilation permettant la transformation d'une application modelisee a haut niveau d'abstraction (UML) vers un modele RTL. En fonction des contraintes de surfaces disponibles (technologie FPGA), le flot de conception optimise le deroulement des boucles et le placement des tâches. Le code VHDL produit est directement simulable et synthetisable sur FPGA. A partir d'applications modelisees en UML, nous produisons automatiquement un code VHDL. Le flot de conception propose a ete utilise avec succes dans le cadre de securite automobile ; un algorithme de detection d'obstacles a ete automatiquement genere depuis sa specification UML.

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