An optimal design of a fault tolerant reversible multiplier

One of the most challenging issues in circuit design is power consumption. Reversible logic is one of the ways for power optimization. In this paper, we propose an optimal design of a fault tolerant reversible n×n multiplier circuit, where n is the number of bits of the operands of multiplier. Two algorithms have been presented to construct the Partial Product Generation (PPG) circuit and the Multi-Operand Addition (MOA) circuit of the proposed multiplier. We also propose a new fault tolerant reversible gate, namely, LMH gate, to produce an optimal multiplier. In addition, several theorems on the numbers of gates, garbage outputs and quantum cost of the fault tolerant reversible multiplier have been presented to show its optimality. The comparative study shows that the proposed design is much better than the existing approaches considering all the efficiency parameters of reversible logic design which includes numbers of gates, garbage outputs, quantum cost and constant inputs; e.g., for a 4×4 multiplier, the proposed design achieves the improvement of 26.32% in terms of number of gates, 12.5% in terms of garbage outputs, 17% in terms of quantum cost and 20.97% in terms of constant inputs over the existing latest approach.

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