Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits

This paper describes a thermal and power-supply tolerant design methodology for pipeline based circuits. It is shown that by making the circuit more tolerant to VDD and temperature (T) instability, even in the presence of process variations, a yield loss reduction is achieved. The goal is to improve signal integrity in the presence of power-supply voltage (VDD) and/or temperature (T) variations, without degrading circuit performance. By using time borrowing techniques, data integrity loss is avoided, and circuit tolerance to VDD and/or temperature variations is enhanced. The methodology is based on a dynamic delay buffer (DDB) block, used to sense VDD/T variations and to induce dynamic clock skews driving a limited subset of key memory elements. Monte Carlo simulations are used to demonstrate that the proposed methodology still holds, even in the presence of process variations.

[1]  João Paulo Teixeira,et al.  Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations , 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

[2]  D. Overhauser,et al.  Full-chip verification of UDSM designs , 1998, ICCAD '98.

[3]  Andrew B. Kahng,et al.  Interconnect optimization strategies for high-performance VLSI designs , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

[4]  Guido Gronthoud,et al.  Power Supply Noise in Delay Testing , 2006, 2006 IEEE International Test Conference.

[5]  Thomas Steinecke,et al.  EMC modeling and simulation on chiplevel , 2001, 2001 IEEE EMC International Symposium. Symposium Record. International Symposium on Electromagnetic Compatibility (Cat. No.01CH37161).

[6]  David Blaauw,et al.  Razor: circuit-level correction of timing errors for low-power operation , 2004, IEEE Micro.

[7]  Sandeep K. Gupta,et al.  Structural delay testing of latch-based high-speed pipelines with time borrowing , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[8]  Gerald E. Sobelman,et al.  Time borrowing in high-speed functional units using skew-tolerant domino circuits , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).