Multiplexer Based Circuit Synthesis with Area-Power Trade-Off

Due to the regularity of implementation, multiplexers are widely used in VLSI circuit synthesis. This paper proposes a technique for decomposing a function into 2-to-1 multiplexers performing area-power tradeoff. To the best of our knowledge this is the first ever effort to incorporate leakage into power calculation for multiplexer based decomposition. With respect to an initial ROBDD (Reduced Ordered Binary Decision Diagram) based representation of the function, the scheme shows more than 30% reduction in area, leakage and switching for the LGSynth91 benchmarks without performance degradation. It also enumerates the trade-offs present in the solution space for different weights associated with these three quantities.

[1]  S. Thompson.  MOS Scaling: Transistor Challenges for the 21st Century , 1998 .

[2]  Saibal Mukhopadhyay,et al.  Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.

[3]  Rolf Drechsler,et al.  Low power optimization technique for BDD mapped circuits , 2001, ASP-DAC '01.

[4]  Santanu Chattopadhyay,et al.  Low power combinational circuit synthesis targeting multiplexer based FPGAs , 2004, 17th International Conference on VLSI Design. Proceedings..

[5]  Ki-Hyun Kim,et al.  Low-power multiplexer decomposition by suppressing propagation of signal transitions , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[6]  Martin D. F. Wong,et al.  Delay minimal decomposition of multiplexers in technology mapping , 1996, DAC '96.

[7]  Mohamed I. Elmasry,et al.  Multi-Threshold CMOS Digital Circuits: Managing Leakage Power , 2003 .

[8]  Chien-Liang Liu,et al.  Low power multiplexer decomposition , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

[9]  Kaushik Roy,et al.  Low-Power CMOS VLSI Circuit Design , 2000 .

[10]  David Blaauw,et al.  Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment , 2005, ASP-DAC '05.

[11]  Mohamed I. Elmasry,et al.  Multi-Threshold CMOS Digital Circuits , 2003 .

[12]  Sheldon B. Akers,et al.  Binary Decision Diagrams , 1978, IEEE Transactions on Computers.

[13]  Alberto Sangiovanni-Vincentelli,et al.  Logic synthesis for vlsi design , 1989 .