A Current-Draining FoldedUp-ConversionMixerand P6 Pre-Amplifier Stage ina CMOS Technology forIEEE 802.1 1a WPAN Applications

Thispaperdescribes a 3.5-GHzup-conversion mixercoreutilized inatwosteptransmitter architecture in compliant withIEEE802.1la WPAN application. Thedesign is basedon current-draining folded architecture. Themain advantage oftheintroduced mixertopology is:highlinearity andmoderate conversion powergain. Themixer isdesigned in a0.18-pm CMOS technology, operating from1.8-Vpower supply. The integrated up-converter and preamplifier consumes SmAand22mAofcurrent respectively from1.8-V supply andshows4.73-dBm OIP3(-1.74-dBm l1P3) and-9.41- dBmP1dBwith5.65dBm ofconversion powergain. IndexTerms-CMOSmixers, folded up-conversion mixers, current draining, lowvoltage.