A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS

Flip-flops (FF) typically consume more than 50% of random-logic power in an SoC chip, due to their redundant transition of internal nodes, when the input and the output are in the same state. Several low-power techniques have been proposed [1–5], but all of them incur transistor-count penalties, leading to an increase in size, which is too costly since flip-flops typically account for 50% of random-logic area. In this work, we design and test a D-flip-flop, known as adaptive-coupling flip-flop (ACFF), which has a reduced transistor count compared to other low-power flip-flops, and 2 fewer transistors than the mainstream transmission-gate flip-flop (TGFF). ACFF features a single-phase clocking structure, with no local clock buffer and no precharging stage, enabling it to be more energy efficient than TGFF, where up to 77% energy saving is achieved at 0% data activity. ACFF also has an adaptive-coupling configuration, which weakens state-retention coupling during a transition, allowing it to be tolerant to process variations. Test chips are fabricated in a 40nm CMOS technology for 1.1V application, and 500k ACFFs are tested over all chips in 5 skew wafers. All tested ACFFs are fully functional down to 0.75V supply voltage, with spreads of timing parameters comparable to TGFF. We also demonstrate a P&R test by employing ACFF to a wireless LAN chip, and the results indicate chip power is reduced by as much as 24%.