Systematic Microwave Network Analysis for Multilayer Printed Circuit Boards With Vias and Decoupling Capacitors

An efficient microwave network method is proposed for signal and power integrity analysis of a multilayer printed circuit board with multiple vias and decoupling capacitors. The multilayer parallel plate structure is described as a cascaded microwave network. The admittance matrix of a single plate pair with ports defined in via holes both on top and bottom plates is obtained through the intrinsic via circuit model and impedance matrix between two plates. A recursive algorithm is provided to obtain the combined admittance matrix of two layers of plate pair coupled through via holes on a common plate. Decoupling capacitors are naturally treated as impedance loads to the cascaded admittance network. Numerical simulations and measurements have been used to validate the method and good agreements have been observed. While the method is as accurate as full-wave numerical solvers, it achieves much higher efficiencies both in CPU time and memory requirements.