On Diagnosing the Aging Level of Automotive Semiconductor Devices

Semiconductor aging is a serious threat to the reliability of a system. We address the aging level of semiconductor components by describing the degree of semiconductor aging under certain operating conditions, including voltage, frequency, temperature, and usage rate. Aging level information can be used to follow the real aging rate of a device, predict the remaining life, and control the device performance under certain degradation conditions by balancing the operation of various device components. Such applications can improve the reliability of automotive semiconductor systems, which should have longer lives than mobile systems. In this brief, we present an aging level estimating flip-flop (FF) that can be used for these and other applications as well. Moreover, we can control the operation of the proposed FF by controlling its clock and control signals. We demonstrate an application of the proposed FF for aging-monitoring, showing that, by halting the operation of the proposed FF, the power consumption is significantly reduced compared with other approaches.

[1]  Hideo Fujiwara,et al.  A Failure Prediction Strategy for Transistor Aging , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Subhasish Mitra,et al.  Gate-Oxide Early Life Failure Prediction , 2008, 26th IEEE VLSI Test Symposium (vts 2008).

[3]  Yu Cao,et al.  Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology , 2007, IEEE Transactions on Device and Materials Reliability.

[4]  Tomokazu Yoneda,et al.  A Scan-Based On-Line Aging Monitoring Scheme , 2014 .

[5]  Mehdi Baradaran Tahoori,et al.  Cross-layer approaches for an aging-aware design of nanoscale microprocessors: Dissertation summary: IEEE TTTC E.J. McCluskey doctoral thesis award competition finalist , 2015, 2015 IEEE International Test Conference (ITC).

[6]  Jari Nurmi,et al.  Improving Reconfigurable Hardware Energy Efficiency and Robustness via DVFS-Scaled Homogeneous MP-SoC , 2011, 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum.

[7]  Subhasish Mitra,et al.  CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns , 2008, 2008 Design, Automation and Test in Europe.

[8]  Jacob A. Abraham,et al.  An aging-aware flip-flop design based on accurate, run-time failure prediction , 2012, 2012 IEEE 30th VLSI Test Symposium (VTS).

[9]  Hiroaki Inoue,et al.  VAST: Virtualization-Assisted Concurrent Autonomous Self-Test , 2008, 2008 IEEE International Test Conference.

[10]  Mehdi Baradaran Tahoori,et al.  Cross-layer resilient system design flow , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

[11]  Toru Nakura,et al.  Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[12]  Wei Wang,et al.  On-Chip Aging Sensor Circuits for Reliable Nanometer MOSFET Digital Circuits , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[13]  Toshinori Sato,et al.  A Simple Flip-Flop Circuit for Typical-Case Designs for DFM , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

[14]  Trevor Mudge,et al.  Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[15]  Tomokazu Yoneda,et al.  A circuit failure prediction mechanism (DART) for high field reliability , 2009, 2009 IEEE 8th International Conference on ASIC.

[16]  Xiaoqing Wen,et al.  On estimation of NBTI-Induced delay degradation , 2010, 2010 15th IEEE European Test Symposium.

[17]  Onur Mutlu,et al.  Operating system scheduling for efficient online self-test in robust systems , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[18]  Ming Zhang,et al.  Circuit Failure Prediction and Its Application to Transistor Aging , 2007, 25th IEEE VLSI Test Symposium (VTS'07).

[19]  Ali M. Niknejad,et al.  BSIM compact MOSFET models for SPICE simulation , 2013, Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2013.