CMOS Domino Logic Circuit for High Speed Performance

In this paper a high speed and low power domino logic circuit is proposed by using voltage divider current mirror technique. To avoid charge leakage and charge sharing problems, domino logic design is used in the circuit due to their advantages such as high speed and less noise immunity. Using this voltage divider current mirror circuit, contention current and power dissipation in the circuit is reduced without affecting the noise immunity of the circuit. With the scaling in technology, performance of digital logic is degrades due to increase in sub-threshold current. This proposed circuit provides very small speed-power product as compared to previously designed domino logic circuits. Simulations are carried out in cadence 90nm technology with supply voltage of 1 volt for the case of OR gate.

[1]  Vojin G. Oklobdzija,et al.  Design-performance trade-offs in CMOS-domino logic , 1986 .

[2]  Christer Svensson,et al.  Noise in digital dynamic CMOS circuits , 1994 .

[3]  Kevin J. Nowka,et al.  Circuit design techniques for a gigahertz integer microprocessor , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

[4]  James T. Kao,et al.  Subthreshold leakage control techniques for low power digital circuits , 2001 .

[5]  Eby G. Friedman,et al.  Low swing dual threshold voltage domino logic , 2002, GLSVLSI '02.

[6]  Atila Alvandpour,et al.  A sub-130-nm conditional keeper technique , 2002, IEEE J. Solid State Circuits.

[7]  Kaushik Roy,et al.  Gate leakage reduction for scaled devices using transistor stacking , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Kaushik Roy,et al.  Diode-footed domino: a leakage-tolerant high fan-in dynamic circuit design style , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[9]  Pinaki Mazumder,et al.  On circuit techniques to improve noise immunity of CMOS dynamic logic , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Kaushik Roy,et al.  A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  N. Tzartzanis,et al.  A Leakage Current Replica Keeper for Dynamic Circuits , 2006, IEEE Journal of Solid-State Circuits.

[12]  Marco Lanuzza,et al.  Low-power split-path data-driven dynamic logic , 2009, IET Circuits Devices Syst..