Hardware Implementation of a High Performance and Low Power DDR2 Controller

Along with the requirements to the bandwidth of SoC internal system bus,it brings the challenges of the high-throughput to a memory controller.For improving the bus bandwidth,we get two considerations.One is to connect the memory controller directly to the major modules which are bandwidth-hungry,and do smart arbitration to these channels so that they can communicate without having to go through the AMBA bus.Even more,designer can use AXI bus to speed up the data transmission between modules in SoC.The other one is to analyze the features of DDR2 SDRAM and design the memory controller with the command scheduler to reduce the read/write cycles,and then it reduce the power consumption of the SoC chip.We also design the auto power down mechanism to reduce energy consumption.This study provides a good idea to improve performance of DDR2 SDRAM controller.