论文信息 - A reconfigurable pipelined ADC in 0.18 /spl mu/m CMOS

A reconfigurable pipelined ADC in 0.18 /spl mu/m CMOS

A reconfigurable pipelined A/D converter has been implemented in a 0.18 /spl mu/m RF-CMOS process. The ADC has eight configurations with a top performance of 10 bits resolution at 80 MSPS consuming 94mW. The reconfigurability is achieved by combining the cyclic and pipelined ADC architectures giving it a low level of complexity. In the conventional pipeline mode, the measured SFDR is 69 dBFS and the SNDR is 56.5 dBc for a 1.54 MHz single sinusoid tone input.

M. Anderson | K. Norling | A. Dreyfert | J. Yuan

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