Advances in multicomputers

Abstract A multicomputer is a distributed memory parallel computing system made of multiple homogeneous or heterogeneous processors. Parallel machines of this kind are highly flexible in their configurations and usages, and are expected to be the mainstream high-performance computing environment of the 1990s. Carnegie Mellon University, with its competitively selected industrial partners, has two research projects in this area. The iWarp ™ project has developed a single-chip building block processor for homogeneous multicomputers. Consisting of approximately 650,000 transistors, the iWarp processor is one of the first high-performance microprocessors specially designed for parallel processing. The Nectar project has developed a high-speed network backplane for heterogeneous multicomputers. The Nectar network is made of fiber-optic links, large crossbar switches, and dedicated network coprocessors. A 26-host Nectar prototype using 100 megabit per second links is supporting research in distributed computing. The next generation Nectar, using 1 gigabit per second or higher speed fiber links, is under development. These two efforts exemplify recent advances in multicomputers. Homogeneous multicomputers can now take advantage of highly integrated processors such as iWarp that have been specially designed to support the fast and flexible interprocessor communication needed in parallel processing. Heterogeneous multicomputers, capable of simultaneously providing different types of computing resources to meet application needs, can now be based on a general high-speed network backplane such as Nectar.

[1]  Charles L. Seitz,et al.  Multicomputers: message-passing concurrent computers , 1988, Computer.

[2]  H. T. Kung.  Why systolic architectures? , 1982, Computer.

[3]  L. W. Tucker,et al.  Architecture and applications of the Connection Machine , 1988, Computer.

[4]  Alain J. Martin,et al.  The architecture and programming of the Ametek series 2010 multicomputer , 1988, C3P.

[5]  H. T. Kung.  Memory requirements for balanced computer architectures , 1985, J. Complex..

[6]  H. T. Kung,et al.  Network-based multicomputers: redefining high performance computing in the 1990s , 1989 .

[7]  Randy H. Katz,et al.  A case for redundant arrays of inexpensive disks (RAID) , 1988, SIGMOD '88.

[8]  William J. Dally,et al.  A VLSI Architecture for Concurrent Data Structures , 1987 .

[9]  Shekhar Y. Borkar,et al.  iWarp: an integrated solution to high-speed parallel computing , 1988, Proceedings. SUPERCOMPUTING '88.

[10]  H. T. Kung,et al.  The Warp Computer: Architecture, Implementation, and Performance , 1987, IEEE Transactions on Computers.

[11]  Monica S. Lam,et al.  Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor , 1989, ASPLOS.

[12]  Randal E. Bryant,et al.  COSMOS: a compiled simulator for MOS circuits , 1987, DAC '87.

[13]  J. A. Webb,et al.  Low-level vision on Warp and the apply programming model. Technical report , 1987 .

[14]  H. T. Kung.  Systolic communication , 1988, [1988] Proceedings. International Conference on Systolic Arrays.

[15]  H. T. Kung,et al.  Comprehensive evaluation of a two-dimensional configurable array , 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[16]  Michael Stonebraker,et al.  A project on high performance I/0 subsystems , 1989, CARN.

[17]  H. T. Kung,et al.  The design of nectar: a network backplane for heterogeneous multicomputers , 1989, ASPLOS 1989.

[18]  Charles L. Seitz,et al.  The cosmic cube , 1985, CACM.

[19]  H. T. Kung,et al.  Applications and Algorithm Partitioning on Warp , 1987, COMPCON.

[20]  Monica Sin-Ling Lam,et al.  A Systolic Array Optimizing Compiler , 1989 .

[21]  Mark Homewood,et al.  The IMS T800 Transputer , 1987, IEEE Micro.

[22]  H. T. Kung,et al.  Systolic Arrays for (VLSI). , 1978 .