Nano CMOS Charge Pump for Readerless RFID PLL

Readerless RFID has become more significant for reliable wireless communication. The Phase Locked Loop (PLL) is among the most crucial functional block in the Readerless RFID where the PLL performance greatly depends on the Charge Pump (CP). Conventional CP circuits suffer from current mismatching characteristics which generate phase offset and spurs in the PLL output signals. To overcome these problems, the CP current mismatch has to be minimized. An enhanced CP circuit with zero current mismatch is presented in this article adopting an ideal current mirror technique and an additional inverter to provide a rail-to-rail voltage. The post-layout simulation shows that the proposed CP maintains the steady current over a wide range of output voltage from 0.1-1.8 V consuming the substantially lower power of 0.178 μW. The CP circuit is designed in 130 nm CMOS process that operates at 1.8 V, and the core occupies 17 x 59.5 μm2. The proposed CP will be a good solution for low voltage, high-frequency PLL structure which suffers from poor performance.

[1]  Md. Torikul Islam Badal,et al.  Advancement of CMOS Transimpedance Amplifier for Optical Receiver , 2019, Transactions on Electrical and Electronic Materials.

[2]  Nam-Soo Kim,et al.  High performance two-stage charge-pump for spur reduction in CMOS PLL , 2014, 2014 IEEE 11th International Multi-Conference on Systems, Signals & Devices (SSD14).

[3]  Kok Swee Leong,et al.  Development of self-powered thermoelectric based RF transmitter circuit , 2016, 2016 IEEE International Conference on Power and Energy (PECon).

[4]  W. Rhee,et al.  Design of high-performance CMOS charge pumps in phase-locked loops , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[5]  Duncan G. Elliott,et al.  High-Efficiency Charge Pumps for Low-Power On-Chip Applications , 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  李智群,et al.  Design of a high performance CMOS charge pump for phase-locked loop synthesizers , 2011 .

[7]  Ankur Sangal,et al.  High speed CMOS charge pump circuit for PLL applications using 90nm CMOS technology , 2011, 2011 World Congress on Information and Communication Technologies.

[8]  José Silva-Martínez,et al.  Design and Analysis of an Ultrahigh-Speed Glitch-Free Fully Differential Charge Pump With Minimum Output Current Variation and Accurate Matching , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[9]  Mark Van Paemel,et al.  Analysis of a charge-pump PLL: a new model , 1994, IEEE Trans. Commun..

[10]  Mamun Bin Ibne Reaz,et al.  Low power high-speed current comparator using 130nm CMOS technology , 2016, 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering (ICAEES).

[11]  Young-Shig Choi,et al.  Gain-Boosting Charge Pump for Current Matching in Phase-Locked Loop , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[12]  Soo-Won Kim,et al.  Digital calibration technique using a signed counter for charge pump mismatch in phase-locked loops , 2013, IET Circuits Devices Syst..

[13]  Adam Zaziabl.  Low power 1 GHz charge pump phase-locked loop in 0.18 µm CMOS process , 2010, Proceedings of the 17th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2010.

[14]  Pankaj Agrawal,et al.  Design of Phase Frequency Detector and Charge Pump for Low Voltage High Frequency PLL , 2014, 2014 International Conference on Electronic Systems, Signal Processing and Computing Technologies.

[15]  Shin-Il Lim,et al.  Charge pump with perfect current matching characteristics in phase-locked loops , 2000 .

[16]  Mohammad Gholami,et al.  A Novel Charge Pump with Low Current for Low-Power Delay-Locked Loops , 2017, Circuits Syst. Signal Process..

[17]  Guillermo Espinosa,et al.  A charge pump with a 0.32 % of current mismatch for a high speed PLL , 2016 .

[18]  Mamun Bin Ibne Reaz,et al.  Low Power High-Efficiency Shift Register Using Implicit Pulse-Triggered Flip-Flop in 130 nm CMOS Process for a Cryptographic RFID Tag , 2016 .

[19]  Kang-Yoon Lee,et al.  A CMOS dual-band fractional-n synthesizer with reference doubler and compensated charge pump , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[20]  P. Larsson,et al.  A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability , 1999, IEEE J. Solid State Circuits.

[21]  Tsutomu Yoshimura,et al.  Analysis of Pull-in Range Limit by Charge Pump Mismatch in a Linear Phase-Locked Loop , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[22]  Siti Aishah Ramli,et al.  Design of a Low-power CMOS Level Shifter for Low-delay SoCs in Silterra 0.13 µm CMOS Process , 2017 .

[23]  Mamun Bin Ibne Reaz,et al.  CMOS Transmitters for 2.4-GHz RF Devices: Design Architectures of the 2.4-GHz CMOS Transmitter for RF Devices , 2019, IEEE Microwave Magazine.

[24]  Ge Wang.  which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Fractal MapReduce decomposition of sequence alignment , 2005 .

[25]  Pui-In Mak,et al.  Self-tracking charge pump for fast-locking PLL , 2010 .