Techniques for the design of parallel and pipelined vlsi systems for numerical computation with special reference to signal processing applications (systolic array, scheduling)

Given an algorithm expressed as, say, a set of difference equations we wish to obtain a complete description of a circuit that executes the given algorithm and can be implemented in VLSI. Let us assume that the circuit will be built from modules that are already defined (either custom-made, or picked out of an existing library). Such "higher level" design issues have not been formalized enough to automate the process. A critical issue is the specification of the times at which each operation of each module is scheduled, and the times at which specific signal values are present at given terminals. To achieve this objective we introduce a scheduling formalism. We show how directed cycles in the flow graph can be handled by a proper interpretation of the concept of iteration. Using this formalism we show how to verify the logical correctness of a given circuit, and how to translate a given flow graph into a logic diagram guaranteed to have the input-output map defined by the flow graph. The scheduling formalism is then used to obtain circuits that are optimal according to several criteria, including smallest sample period, smallest latency, and smallest register count. Scheduling under resource constraints is briefly considered. Multiprocessor arrays are a class of implementations that are of particular value for signal processing and other such "regular" algorithms. The second half of the thesis studies the properties of such arrays and shows how to exploit regularity to greatly reduce the amount of work that has to be done to determine how well an algorithm is suited for parallel implementation. A class of "regular iterative algorithms" is introduced that is well-suited for implementation on such arrays. Properties of such algorithms are studied and a systematic translation procedure provided.