The quarter micron challenge: intergrating physical and logic design

Device size continues to shrink, enabling exponential growth in microelectronics. Density (number of devices / area) is increasing by an order of magnitude every 6 years and speed (clock frequency in synchronous designs) is increasing by an order of magnitude every 8 years. Currently, the bulk of the ASIC industry is using technology around 0.5 microns, while advanced designs already use 0.35, 0.25 and even 0.18 micron. As device size approaches quarter micron and below, certain physical effects become more important. Most noticeably, interconnect delay becomes dominant, power becomes more of a limiting factor and signal integrity issues can no longer be ignored. This presentation explores the consequences of the above trends for EDA. The prevalent ASIC (standard cell or gate array) design methodology is based on simulation and synthesis of an RTL description, placement and routing, extraction, back-annotation and physical verification. For technologies around and below 0.5 micron some iteration between logic synthesis and placement and routing becomes necessary. Essentially, physical information like the placement (at the floorplan or at the individual cell level) is fed back to logic synthesis to enable more accurate wire load models and partial re-synthesis (sizing, buffering, IPO, etc.). This methodology becomes less feasible as the effects described above become more severe. The emerging solutions for quarter micron and below mostly involve the following elements. Floor planning provides early placement information for synthesis and allows the co-development of the logical and physical designs. A floor planner must be able to deal with large blocks such as memories and cores and also to accommodate custom logic. Large designs demand hierarchy and mixing of black boxes, coarsely placed blocks and detailed placed blocks. To perform wireability analysis (congestion) and accurate delay estimation of the interconnect, an integrated global router is required. To calculate the delays at all stages of the design, a flexible, chiplevel static timing analysis tool is necessary. Time budgeting is also essential. Finally, logic synthesis and physical design must be integrated more tightly. Algorithmically, this means that placement and certain logic optimizations such as buffer insertion, sizing and critical path optimization could be performed together. From a software engineering point of view, this means a common infrastructure which allows easy and fast communication of data, avoiding unnecessary duplications. We can expect profound changes in design methodology over the coming years. The industry will need to retool to cope with the changes in technology and design, opening new opportunities for research, tool development and consulting in EDA.