Undetectable fault removal of sequential circuits based on unreachable states

We present a procedure to reduce sequential circuits by removing undetectable faults based on unreachable states. Procedures for obtaining unreachable stares and for identifying undetectable faults which can be the target of fault removal are presented. Experimental results for ISCAS benchmark circuits are shown.

[1]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[2]  Vishwani D. Agrawal,et al.  Combinational ATPG theorems for identifying untestable faults in sequential circuits , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Masahiro Fujita,et al.  Boolean resubstitution with permissible functions and binary decision diagrams , 1991, DAC '90.

[4]  Irith Pomeranz,et al.  Classification of Faults in Synchronous Sequential Circuits , 1993, IEEE Trans. Computers.

[5]  Fabio Somenzi,et al.  Redundancy identification/removal and test generation for sequential circuits using implicit state enumeration , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  On identifying undetectable and redundant faults in synchronous sequential circuits , 1994, Proceedings of IEEE VLSI Test Symposium.

[7]  Irith Pomeranz,et al.  On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences , 1996, IEEE Trans. Computers.

[8]  M. S. Harris.  Digital systems testing and testable design: M. Abramovici, M.A. Breur and A.D. Friedman. Computer Science Press, New York, 1991, 652 pp., £43.95 , 1992 .

[9]  Kwang-Ting Cheng,et al.  Redundancy removal for sequential circuits without reset states , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Carl Pixley,et al.  A theory and implementation of sequential hardware equivalence , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[12]  Kozo Kinoshita,et al.  Synthesis of Sequential Circuits by Redundancy Removal and Retiming , 1997, J. Electron. Test..

[13]  David E. Long,et al.  Identifying sequentially untestable faults using illegal states , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[14]  Miron Abramovici,et al.  Sequentially untestable faults identified without search ("simple implications beat exhaustive search!") , 1994, Proceedings., International Test Conference.

[15]  Kozo Kinoshita,et al.  Removal of redundancy in logic circuits under classification of undetectable faults , 1992, [1992] Digest of Papers. FTCS-22: The Twenty-Second International Symposium on Fault-Tolerant Computing.