Optimized nickel silicide process formation for high performance sub-65nm CMOS nodes

Nickel silicide is an important material for sub-65nm advanced technology devices. Typically, the silicide can be formed by a single annealing step, which provides the low resistivity NiSi phase. This is followed by selective etching of the unreacted nickel, which results in functional CMOS devices. In this paper, we show that a process sequence employing two annealing steps is mandatory to obtain the best results. Indeed, we demonstrate for the first time that only a low temperature RTA1 can avoid electrical bridging between the source and the gate and also avoid excessive nickel injection into the active zone and polysilicon gate. Thus, the narrow line effect and junction leakage are both much reduced.