论文信息 - A 0.35 /spl mu/m ECL-CMOS process technology on SOI for 1 ns mega-bits SRAMs with 40 ps gate array

A 0.35 /spl mu/m ECL-CMOS process technology on SOI for 1 ns mega-bits SRAMs with 40 ps gate array

A 0.35 /spl mu/m ECL-CMOS technology has been developed to achieve high speed and high density LSIs for mainframe computers. A high speed bipolar transistor with cutoff frequency f/sub T/ of 30 GHz and a 30 /spl mu/m/sup 2/ 6T-CMOS memory cell with a trench isolation are introduced onto an SOI substrate. This technology has been applied to a 40 ps, 120 K gate logic LSI and a 1 ns, 2.3 Mbit SRAM with 50 K gate array.

[1] T. Hiramoto,et al. A 27 GHz double polysilicon bipolar technology on bonded SOI with embedded 58 mu m/sup 2/ CMOS memory cells for ECL-CMOS SRAM applications , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[2] Masayuki Ohayashi,et al. A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates , 1994 .