Circuit partitioning and resynthesis

A circuit partitioning method based on analysis of reconvergent fanout is introduced. A DAG model for a circuit is considered. A corolla is defined as a set of overlapping reconvergent fanout regions. The DAG is partitioned into a set of nonoverlapping corollas, and the corollas are used to resynthesize the circuit. It is shown that resynthesis of large benchmark circuits consistently reduces transistor pairs and layout area, while improving delay and testability.<<ETX>>

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