Sequence Length , Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST

For the first time, we study the coverage of non-target defects for Deterministic Logic BIST (DLBIST) architecture. We consider several DLBIST implementation options that result in test sequences of different lengths. Resistive brid ging faults are used as a surrogate of non-target defects. Experi mental data obtained for largest ISCAS benchmarks suggests that, although DLBIST always guarantees complete stuck-at coverage, test sequence length does influence the non-targe t defect detection capabilities. For circuits with a large fr action of random-pattern resistant faults, the embedded dete rministic patterns as well as a sufficient amount of random patterns are both demonstrated to be essential for non-targ e defect detection. It turns out, moreover, that area cost is lower for DLBIST solutions with longer test sequences, due to additional degrees of freedom for the embedding procedure and a lower number of faults undetected by pseudorandom patterns. This implies that DLBIST is particularly effective in covering non-target defects.

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