Design and analysis of segmented routing channels for row-based FPGA's

FPGA's combine the logic integration benefits of custom VLSI with the design, production, and time-to-market advantages of standard logic IC's. The Actel family of FPGA's exemplifies the row-based FPGA model. Rows of logic cells interspersed with routing channels have given this family of FPGA devices the flavor of traditional channeled gate arrays or standard cells. However, unlike the conventional standard cell design, the FPGA routing channels contain predefined wiring segments of various lengths that are interconnected using antifuses. This paper develops analytical models that permit the design of FPGA channel architecture and the analysis of the routability of row-based FPGA devices based on a generic characterization of the row-based FPGA routing algorithms. In particular, it demonstrates that using probabilistic models for the origination point and length of connections, an FPGA with properly designed segment length and distribution can be nearly as efficient as a mask-programmable channel (in terms of the number of required tracks). Experimental results corroborate this prediction. This paper does not address specifics of the routing algorithms, but investigates the design of the channel segmentation architecture (i.e., various lengths and patterns of segments and connections among these segments) in order to increase the probability of successful routing. >