Distributed sleep transistor network for power reduction

Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the simultaneous switching current per cluster and then inserting a sleep transistor per cluster. In the paper, we propose a novel distributed sleep transistor network (DSTN), and show that DSTN is intrinsically better than the cluster-based design in terms of the sleep transistor area and circuit performance. We reveal properties of optimal DSTN designs, and then develop an efficient algorithm for gate level DSTN synthesis. The algorithm obtains DSTN designs with up to 70.7% sleep transistor area reduction compared to cluster-based designs. Furthermore, we present custom layout designs to verify the area reduction by DSTN.

[1]  Satoshi Shigematsu,et al.  A 1-V multithreshold-voltage CMOS digital signal processor for mobile phone application , 1996, IEEE J. Solid State Circuits.

[2]  Ibrahim N. Hajj,et al.  Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Jinjun Xiong,et al.  On optimal physical synthesis of sleep transistors , 2004, ISPD '04.

[4]  Kwang-Ting Cheng,et al.  Estimation for maximum instantaneous current through supply lines for CMOS circuits , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[5]  Sheldon X.-D. Tan,et al.  Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings , 1999, DAC '99.

[6]  Ibrahim N. Hajj,et al.  Improved delay and current models for estimating maximum currents in CMOS VLSI circuits , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[7]  Lei He,et al.  Leakage power modeling and reduction with data retention , 2002, ICCAD 2002.

[8]  Ishiuchi,et al.  Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas , 2004 .

[9]  Shin'ichiro Mutoh,et al.  1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS , 1995, IEEE J. Solid State Circuits.

[10]  Lei He,et al.  Distributed sleep transistor network for power reduction , 2003, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Stephen P. Boyd,et al.  Design of robust global power and ground networks , 2001, ISPD '01.

[12]  Anantha Chandrakasan,et al.  MTCMOS hierarchical sizing based on mutual exclusive discharge patterns , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[13]  Sheldon X. D. Tan,et al.  Efficient VLSI Power/Ground Network Sizing Based on Equivalent Circuit Modeling , 2003 .

[14]  Massoud Pedram,et al.  Ground bounce in digital VLSI circuits , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[15]  Kwang-Ting Cheng,et al.  Estimation of maximum power supply noise for deep sub-micron designs , 1998, ISLPED '98.

[16]  S. Chowdhury,et al.  Estimation of maximum currents in MOS IC logic circuits , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Suhwan Kim,et al.  Understanding and minimizing ground bounce during mode transition of power gating structures , 2003, ISLPED '03.

[18]  James Kao,et al.  Subthreshold leakage modeling and reduction techniques , 2002, ICCAD 2002.

[19]  H. Morimura,et al.  A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM: with charge-recycling input/output buffers , 1999 .

[20]  Mohamed I. Elmasry,et al.  Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique , 2002, DAC '02.

[21]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[22]  Yi-Min Jiang,et al.  Estimation of maximum power and instantaneous current using a genetic algorithm , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

[23]  S. Chowdhury.  Optimum Design of Reliable IC Power Networks Having General Graph Topologies , 1989, 26th ACM/IEEE Design Automation Conference.

[24]  Kwang-Ting Cheng,et al.  Vector generation for maximum instantaneous current through supply lines for CMOS circuits , 1997, DAC.

[25]  Sani R. Nassif,et al.  Congestion-driven codesign of power and signal networks , 2002, DAC '02.