CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation
暂无分享,去创建一个
[1] Kevin Skadron,et al. Control-theoretic techniques and thermal-RC modeling for accurate and localized dynamic thermal management , 2002, Proceedings Eighth International Symposium on High Performance Computer Architecture.
[2] Kaushik Roy,et al. Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability , 2005, 14th Asian Test Symposium (ATS'05).
[3] Luciano Lavagno,et al. Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool , 1995, 32nd Design Automation Conference.
[4] Kaushik Roy,et al. Statistical timing analysis using levelized covariance propagation , 2005, Design, Automation and Test in Europe.
[5] S. Naffziger,et al. Power and temperature control on a 90-nm Itanium family processor , 2006, IEEE Journal of Solid-State Circuits.
[6] D. J. Hathaway,et al. Uncertainty-aware circuit optimization , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).
[7] Vivek De,et al. Design and reliability challenges in nanometer technologies , 2004, Proceedings. 41st Design Automation Conference, 2004..
[8] David Blaauw,et al. Statistical optimization of leakage power considering process variations using dual-Vth and sizing , 2004, Proceedings. 41st Design Automation Conference, 2004..
[9] Kaushik Roy,et al. A novel synthesis approach for active leakage power reduction using dynamic supply gating , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[10] Jan M. Rabaey,et al. Digital Integrated Circuits , 2003 .
[11] David Blaauw,et al. Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation , 2003, MICRO.
[12] Kaushik Roy,et al. Novel sizing algorithm for yield improvement under process variation in nanometer technology , 2004, Proceedings. 41st Design Automation Conference, 2004..
[13] Kevin Skadron,et al. Temperature-Aware Microarchitecture: Extended Discussion and Results , 2003 .
[14] Sudhakar M. Reddy,et al. Design of robustly testable combinational logic circuits , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..