论文信息 - A Multi-Core AES Cryptoprocessor for Multi-Channel SDR

A Multi-Core AES Cryptoprocessor for Multi-Channel SDR

This paper presents a multi-core architecture for cryptographic processors. This architecture is specially designed for use in multi-channel Software Defined Radio Device. It provides support for GCM, CCM, CTR and other block cipher modes applied to AES algorithm. It can reach a maximum throughput around 2 Gbps. This paper also presents how partial reconfiguration could be used to improve flexibility of multi-core cryptoprocessors.

Lilian Bossuet | Guy Gogniat | Dominique Dallet | Bertrand Le Gal | Michael Grand

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