Increasing Functionality of Wafer’s Backside: Analysis of Si and WS₂ Backside Power-Switch
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G. Mirabelli | J. Ryckaert | P. Weckx | G. Hellings | G. Hiblot | R. Chen | O. Zografos | B. Chehab | Z. Ahmed
[1] I. Radu,et al. Wafer-Scale Bi-Assisted Semi-Auto Dry Transfer and Fabrication of High-Performance Monolayer CVD WS2 Transistor , 2022, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).
[2] I. Radu,et al. Perspective on Low-dimensional Channel Materials for Extremely Scaled CMOS , 2022, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).
[3] A. Jourdain,et al. Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node , 2022, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).
[4] F. M. Bufler,et al. PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch , 2022, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).
[5] K. Saraswat,et al. Sub-200 Ω·µm Alloyed Contacts to Synthetic Monolayer MoS2 , 2021, International Electron Devices Meeting.
[6] C. Rogan,et al. Advancing 2D Monolayer CMOS Through Contact, Channel and Interface Engineering , 2021, 2021 IEEE International Electron Devices Meeting (IEDM).
[7] S. Liew,et al. Antimony Semimetal Contact with Enhanced Thermal Stability for High Performance 2D Electronics , 2021, 2021 IEEE International Electron Devices Meeting (IEDM).
[8] G. Beyer,et al. 3D SoC integration, beyond 2.5D chiplets , 2021, 2021 IEEE International Electron Devices Meeting (IEDM).
[9] E. Beyne,et al. Power from Below: Buried Interconnects Will Help Save Moore's Law , 2021, IEEE Spectrum.
[10] A. Jourdain,et al. Enabling Logic with Backside Connectivity via n-TSVs and its Potential as a Scaling Booster , 2021, 2021 Symposium on VLSI Technology.
[11] T. Schram,et al. Introducing 2D-FETs in Device Scaling Roadmap using DTCO , 2020, 2020 IEEE International Electron Devices Meeting (IEDM).
[12] T. Schram,et al. Wafer-scale integration of double gated WS2-transistors in 300mm Si CMOS fab , 2020, 2020 IEEE International Electron Devices Meeting (IEDM).
[13] F. M. Bufler,et al. Monte Carlo Comparison of n-Type and p-Type Nanosheets With FinFETs: Effect of the Number of Sheets , 2020, IEEE Transactions on Electron Devices.
[14] G. Pourtois,et al. ATOMOS: An ATomistic MOdelling Solver for dissipative DFT transport in ultra-scaled HfS2 and Black phosphorus MOSFETs , 2019, 2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
[15] Shien-Yang Wu,et al. Demonstration of a sub-0.03 um2 high density 6-T SRAM with scaled bulk FinFETs for mobile SOC applications beyond 10nm node , 2016, 2016 IEEE Symposium on VLSI Technology.
[16] Pragya Kushwaha,et al. BSIM-CMG: Standard FinFET compact model for advanced circuit design , 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).
[17] Chenming Hu,et al. BSIM-IMG: A Turnkey compact model for fully depleted technologies , 2012, 2012 IEEE International SOI Conference (SOI).
[18] Chung-Hsun Huang,et al. A fast wake-up power gating technique with inducing a balanced rush current , 2012, 2012 IEEE International Symposium on Circuits and Systems.