Increasing Functionality of Wafer’s Backside: Analysis of Si and WS₂ Backside Power-Switch

Recent technological advancements have shown the potential benefits of a backside power-delivery network. Bringing the power much closer to the active logic reduces power consumption, while guaranteeing more routing resources on the top of the wafer. However, backside power delivery also opens new possibilities to further optimize the power consumption and increase functionalities of an IC design. In this work, we report on the increased functionality of wafer’s backside by evaluating different backside power-switch concepts as active backside components. Due to the free area on the backside, area requirements can be relaxed, allowing for iso-power and/or iso-performance optimization with respect to frontside power-switches. Si and WS<sub>2</sub> are considered as candidate materials. Si-based backside power-switches show up to <inline-formula> <tex-math notation="LaTeX">$3.5\times $ </tex-math></inline-formula> less power at iso-performance, while WS<sub>2</sub> more than <inline-formula> <tex-math notation="LaTeX">$10\times $ </tex-math></inline-formula>. For a careful study of WS<sub>2</sub>, both mobility and Schottky barrier are varied. Even in degraded conditions, WS<sub>2</sub>-based backside power-switches can outperform Si ones, at iso-performance and iso-power condition. This work shows a clear window of opportunity for the increase functionality of the wafer’s backside, as well as the heterogeneous integration of novel material with advanced Si logic.

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