An offset-cancelling four-phase voltage sense amplifier for resistive memories in 14nm CMOS

This paper presents a low-offset read sensing scheme for resistive memories. Due to increasing device variations in sub-32 nm CMOS processes, it becomes very challenging to design a high yield and low-offset read-sensing scheme. In this work we address these issues by using a pseudo-differential sensing scheme to get 2× signal margin and by full offset cancellation of the sense-amplifier, making it more suitable to tolerate variation from the memory array due to storage device resistance variation. Measurement results show the sense-amplifier can work with a 20mV input, which makes it ideal for small-signal sensing for resistive memories.

[1]  Yangyin Chen,et al.  ReRAM technology evolution for storage class memory application , 2016, 2016 46th European Solid-State Device Research Conference (ESSDERC).

[2]  Naveen Verma,et al.  A High-Density 45 nm SRAM Using Small-Signal Non-Strobed Regenerative Sensing , 2008, IEEE Journal of Solid-State Circuits.

[3]  Yu Lu,et al.  Fully functional perpendicular STT-MRAM macro embedded in 40 nm logic for energy-efficient IOT applications , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[4]  Doris Schmitt-Landsiedel,et al.  Time-differential sense amplifier for sub-80mV bitline voltage embedded STT-MRAM in 40nm CMOS , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[5]  David Blaauw,et al.  13.7 A reconfigurable sense amplifier with auto-zero calibration and pre-amplification in 28nm CMOS , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[6]  Chankyung Kim,et al.  7.4 A covalent-bonded cross-coupled current-mode sense amplifier for STT-MRAM with 1T1MTJ common source-line structure array , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.