X-compact: an efficient response compaction technique

X-Compact is an X-tolerant test response compaction technique. It enables up to exponential reduction in the test response data volume and the number of pins required to collect test response from a chip. The compaction hardware requires negligible area, does not add any extra delay during normal operation, guarantees detection of defective chips even in the presence of unknown logic values (often referred to as X's), and preserves diagnosis capabilities for most practical scenarios. The technique has minimum impact on current design and test flows, and can be used to reduce test time, test-data volume, test-input/output pins and tester channels, and also to improve test quality.

[1]  Mark G. Karpovsky,et al.  Testing Computer Hardware through Data Compression in Space and Time , 1983, ITC.

[2]  Eiji Fujiwara,et al.  Error-control coding for computer systems , 1989 .

[3]  D. Burek,et al.  Test data compression , 2003, IEEE Design & Test of Computers.

[4]  Ajay Khoche,et al.  Test vector compression using EDA-ATE synergies , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[5]  Brion L. Keller,et al.  A SmartBIST variant with guaranteed encoding , 2001, Proceedings 10th Asian Test Symposium.

[6]  Krishnendu Chakrabarty Zero-aliasing space compaction using linear compactors with bounded overhead , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  John E. Bauer,et al.  An Advanced Fault Isolation System for Digital Logic , 1975, IEEE Transactions on Computers.

[8]  Nilanjan Mukherjee,et al.  Embedded deterministic test for low cost manufacturing test , 2002, Proceedings. International Test Conference.

[9]  Janak H. Patel,et al.  Application of Saluja-Karpovsky compactors to test responses with many unknowns , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[10]  Brion L. Keller,et al.  OPMISR: the foundation for compressed ATPG vectors , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[11]  Subhasish Mitra,et al.  XMAX: X-tolerant architecture for MAXimal test compression , 2003, Proceedings 21st International Conference on Computer Design.

[12]  Minesh B. Amin,et al.  Efficient compression and application of deterministic patterns in a logic BIST architecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[13]  Edward J. McCluskey,et al.  Multiple-output propagation transition fault test , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[14]  Ajay Khoche,et al.  Packet-based input test data compression techniques , 2002, Proceedings. International Test Conference.

[15]  Edward J. McCluskey,et al.  Parallel Signatur Analysis Design with Bounds on Aliasing , 1997, IEEE Trans. Computers.

[16]  Edward J. McCluskey,et al.  Logic design principles - with emphasis on testable semicustom circuits , 1986, Prentice Hall series in computer engineering.

[17]  John P. Hayes,et al.  Optimal space compaction of test responses , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[18]  Erik H. Volkerink,et al.  Efficient seed utilization for reseeding based compression [logic testing] , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[19]  Janak H. Patel,et al.  Reducing test application time for full scan embedded cores , 1999, Digest of Papers. Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing (Cat. No.99CB36352).

[20]  Steven S. Lumetta,et al.  X-codes: error control with unknowable inputs , 2003, IEEE International Symposium on Information Theory, 2003. Proceedings..

[21]  Subhasish Mitra,et al.  Efficient Seed Utilization for Reseeding based Compression , 2003 .

[22]  Edward J. McCluskey,et al.  Stuck-fault tests vs. actual defects , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[23]  Thomas W. Williams,et al.  Design of compactors for signature-analyzers in built-in self-test , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[24]  Nur A. Touba,et al.  Bit-fixing in pseudorandom sequences for scan BIST , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..