Capacitive-resistive nondriven plateline cell architecture for RRAM technology

Abstract A new memory cell concept, which is appropriate for the use with resistive hysteretic memory elements is introduced. Resistive memories are one of the main memory development streams today. The introduced concept can be used to facilitate the integration with current CMOS technology, where no plateline is required. This is accomplished by using a capacitor, which is serially connected to the resistive element.