Advanced Verification Techniques Based on Learning

Design verification poses a very practical problem during circuit synthesis. Learning based verification techniques prove to be an attractive option for verifying two circuits with internal gates having simple functional relationships. We present a verification method which employs a learning technique based on symbolic manipulation and which can more efficiently learn indirect implications. The method can also learn some useful functional implications. We also present a framework in which an indirect implication technique is integrated with an OBDD based verification tool. We present highly efficient verification results on some ISCAS circuits as well as on some very hard industrial circuits.

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