A 6.4Gb/s near-ground single-ended transceiver for dual-rank DIMM memory interface systems
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Yi Lu | Lei Luo | Barry Daly | Bill Stonecypher | Teva Stone | Michael Bucher | Ravi Kollipara | Nhat Nguyen | Wayne D. Dettloff | John C. Eble | Kambiz Kaviani | Chris J. Madden | Bruce Su | Kashinath Prabhu | Pravin Kumar Venkatesan | Fred Heaton | Michael Bucher | J. Eble | K. Kaviani | Bruce Su | B. Daly | B. Stonecypher | W. Dettloff | T. Stone | K. Prabhu | P. Venkatesan | F. Heaton | R. Kollipara | Yi Lu | C. Madden | L. Luo | N. Nguyen
[1] M. Horowitz,et al. A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS , 2007, IEEE Journal of Solid-State Circuits.
[2] Ting Wu,et al. A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface , 2009, IEEE Journal of Solid-State Circuits.
[3] Michael Bucher,et al. A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling , 2010, IEEE Journal of Solid-State Circuits.
[4] Ting Wu,et al. A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface , 2012, IEEE Journal of Solid-State Circuits.
[5] Mark Horowitz,et al. Rethinking DRAM Power Modes for Energy Proportionality , 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.
[6] Amir Amirkhany,et al. A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration , 2012, 2012 IEEE International Solid-State Circuits Conference.