Slack-aware opportunistic monitoring for real-time systems

Recent studies have shown that run-time monitoring is a promising approach for improving the security and reliability of computer systems. In this paper, we present a framework and architecture for applying run-time monitoring to hard real-time systems. In this framework, monitoring is only performed when enough dynamic slack exists in order to ensure that the monitoring does not impact the timing guarantees of tasks. If the slack is insufficient, a dropping operation is run which minimizes the timing impact on the task while ensuring that no false positives occur. We present a novel hardware architecture that can perform this dropping operation in a single cycle, matching the throughput of the task being monitored. Thus, run-time monitoring is able to be applied opportunistically, with no impact on the worst-case execution time of tasks. Our experimental results for three different monitoring techniques verify that timing is never violated and that false positives never occur. In addition, on average, 15-66% of monitoring coverage is achieved with no impact on the worst-case execution times of tasks depending on the monitoring technique. With an FPGA-based monitor, this average coverage of monitoring ranged from 62-86% depending on the monitoring technique.

[1]  Wang Yi,et al.  Combining Abstract Interpretation with Model Checking for Timing Analysis of Multicore Software , 2010, 2010 31st IEEE Real-Time Systems Symposium.

[2]  Francisco J. Cazorla,et al.  Hardware support for WCET analysis of hard real-time multicore systems , 2009, ISCA '09.

[3]  Peter Marwedel,et al.  A Unified WCET Analysis Framework for Multi-core Platforms , 2012, 2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium.

[4]  Cheng Wang,et al.  LIFT: A Low-Overhead Practical Information Flow Tracking System for Detecting Security Attacks , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[5]  G. Edward Suh,et al.  High-performance parallel accelerator for flexible and efficient run-time monitoring , 2012, IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012).

[6]  Jakob Engblom,et al.  The worst-case execution-time problem—overview of methods and survey of tools , 2008, TECS.

[7]  H.-H.S. Lee,et al.  An Integrated Framework for Dependable and Revivable Architectures Using Multicore Processors , 2006, ISCA 2006.

[8]  Eric Rotenberg,et al.  Enforcing safety of real-time schedules on contemporary processors using a virtual simple architecture (VISA) , 2004, 25th IEEE International Real-Time Systems Symposium.

[9]  Krste Asanovic,et al.  Mondrian memory protection , 2002, ASPLOS X.

[10]  Todd M. Austin,et al.  Testudo: Heavyweight security analysis via statistical sampling , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

[11]  Gary S. Tyson,et al.  Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).

[12]  David Broman,et al.  A PRET microarchitecture implementation with repeatable timing and competitive performance , 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).

[13]  Somayeh Sardashti,et al.  The gem5 simulator , 2011, CARN.

[14]  Jan Gustafsson,et al.  The Mälardalen WCET Benchmarks: Past, Present And Future , 2010, WCET.

[15]  David Zhang,et al.  Secure program execution via dynamic information flow tracking , 2004, ASPLOS XI.

[16]  G. Edward Suh,et al.  Worst-case execution time analysis for parallel run-time monitoring , 2012, DAC Design Automation Conference 2012.

[17]  Lui Sha,et al.  Using Simplicity to Control Complexity , 2001, IEEE Softw..

[18]  Alessandro Orso,et al.  Effective memory protection using dynamic tainting , 2007, ASE '07.

[19]  Eric Rotenberg,et al.  Virtual simple architecture (VISA): exceeding the complexity limit in safe real-time systems , 2003, ISCA '03.

[20]  Babak Falsafi,et al.  Flexible Hardware Acceleration for Instruction-Grain Program Monitoring , 2008, 2008 International Symposium on Computer Architecture.

[21]  Hovav Shacham,et al.  The geometry of innocent flesh on the bone: return-into-libc without function calls (on the x86) , 2007, CCS '07.

[22]  G. Edward Suh,et al.  Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.

[23]  Rajiv Gupta,et al.  Dynamic Information Flow Tracking on Multicores , 2008 .

[24]  Hsien-Hsin S. Lee,et al.  An Integrated Framework for Dependable and Revivable Architectures Using Multicore Processors , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).

[25]  Jung Ho Ahn,et al.  McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[26]  Gerard J. M. Smit,et al.  A mathematical approach towards hardware design , 2010, Dynamically Reconfigurable Architectures.

[27]  Radu Grosu,et al.  Software monitoring with controllable overhead , 2010, International Journal on Software Tools for Technology Transfer.

[28]  Lui Sha,et al.  SecureCore: A multicore-based intrusion detection architecture for real-time embedded systems , 2013, 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS).

[29]  Albert Meixner,et al.  Argus: Low-Cost, Comprehensive Error Detection in Simple Cores , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).