With the scaling of the CMOS technology, domino logic circuits experience larger leakage currents, which affect their robustness and performance. The leakage can be compensated by using a properly sized PMOS keeper transistor, at the cost of circuit delay increase. Hence, it is expected that the performance improvement of domino logic will stop in future technology nodes, due to increased required keeper size to maintain robustness. In this paper, we will study different methods of keeper sizing for comparing the performance of CMOS-OR domino logic circuits designed using Predictive Technology models of 32nm, 22nm and 16nm CMOS technology nodes. The keeper size will be adjusted to obtain the same robustness (noise immunity) across the technology generations. With this method of keeper sizing across technology nodes, the simulation results shows that indeed the delay of a low fan-in domino circuit increases from 32nm to 22nm node and the domino circuits fail to operate at 16nm node. For a high fan-in domino gate, however, the delay reduces from 32nm to 22nm; and the circuit fails at 16nm.
[1]
K. Soumyanath,et al.
Robustness of sub-70 nm dynamic circuits: analytical techniques and scaling trends
,
2001,
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).
[2]
Ram Krishnamurthy,et al.
Leakage control techniques for designing robust, low power wide-OR domino logic for sub-130nm CMOS technologies
,
2004,
International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).
[3]
Kaushik Roy,et al.
Diode-footed domino: a leakage-tolerant high fan-in dynamic circuit design style
,
2004,
IEEE Transactions on Circuits and Systems I: Regular Papers.