Clustering analyzer

A VLSI architecture for implementing the squared-error clustering technique using extensive pipelining and parallel techniques is presented. The proposed architecture performs one pass of the squared-error algorithm, which includes finding the squared distances between every pattern and every cluster center, assigning each pattern to its closest cluster center, and recomputing the cluster centers in O(N+M+K) time units, where M is the dimension of the feature vector, N is the number of sample patterns, and K is the desired number of clusters. It needs O(N*M* K) time units if a uniprocessor is used. >