Design of Cascaded PADDL for DPA-Resistant Secure Integrated Circuits Using Penta Magnetic Tunnel Junction

A novel design methodology is to implement a secure DPA resistant crypto secured processor such as advanced encryption standard (AES) and triple data encryption standard (DES), by secure side-channel attacks, such as differential power analysis (DPA). The methodology is suitable for integration in a common automated standard cell ASIC or FPGA design flow. Dynamic logic is obfuscates the output waveforms and the circuit operation, which reducing the effectiveness of the DPA attack for mitigating DPA attacks for applications of secure integrated circuit (IC) design. A Penta MTJ gate that provides self-referencing, simple cascading, less voltage headroom downside in pre charge sense electronic equipment and low space. These types of gate is implemented in (PADDL). Different logic gates and different writing circuitry is required, but the sensing portion is remains same. Therefore, the information is deposited in the pinned layers using series or parallel combinations of transistors as per the logic storing in the Penta MTJ. The logic gate is authenticated by simulation at the 22nm technology node using a tanner tool.