Modeling and Layout Optimization for On-chip Inductive Coupling

In this paper, we study the modeling and layout optimization for on-chip interconnect structures to minimize the inductive coupling. We first investigate the characteristics of mutual (as well as self) inductance for coplanar, micro-stripline, and stripline structures, and examine the effectiveness of design freedoms such as wire sizing, spacing, and shielding. We then propose formula-based models as the figures of merit for inductive coupling in the three interconnect structures, and apply the proposed models to automatically synthesize on-chip interconnect structures. Experiments show that compared to the coupling coefficients computed by a numerical field solver, the models have about 15% difference for coplanar structures, and have negligible difference for micro-stripline and stripline structures. In addition, interconnect structures meeting given noise specifications can be synthesized instantly using proposed models.