A 1.8 $\mu$ W −65 dB THD ECG Acquisition Front-End IC Using a Bandpass Instrumentation Amplifier With Class-AB Output Configuration

This brief presents a power-efficient, highly linear front-end (FE) integrated circuit (IC) for electrocardiogram (ECG) acquisition applications. Compared to typical FE architectures, the proposed FE uses only one bandpass instrumentation amplifier (IA) to reduce the chip area and dc power consumption. To achieve high linearity, the bandpass IA is composed of a high-gain two-stage amplifier in a capacitive-feedback configuration. Miller compensation and the class-AB output stage are utilized to incorporate the filtering and buffering functions within the IA without the need for additional circuit stages. The FE IC is fabricated in 0.13-<inline-formula> <tex-math notation="LaTeX">${ \mu }\text{m}$ </tex-math></inline-formula> CMOS technology, and occupies only a 0.16-mm² chip area. The measured input-referred noise is 3.2 <inline-formula> <tex-math notation="LaTeX">${ \mu }$ </tex-math></inline-formula>Vrms with a midband gain of 34.6 dB, and a bandwidth that extends from 0.9 to 350 Hz. A total harmonic distortion of −65 dB is measured at an input signal of 5.5 mV<inline-formula> <tex-math notation="LaTeX">$_{{pp}}$ </tex-math></inline-formula>, with a dc power consumption of 1.8 <inline-formula> <tex-math notation="LaTeX">${\mu }\text{W}$ </tex-math></inline-formula>. In a real-time measurement, the proposed FE IC is capable of detecting high-fidelity ECG waveforms.