Leveraging partial dynamic reconfiguration on Zynq SoC FPGAs

The ability of modern FPGAs to change isolated regions of their configuration during run-time is increasingly appreciated by industry. Integrating powerful microprocessors modern FPGAs evolved to efficient SoC architectures, making dynamic partial reconfiguration accessible in various ways. Nonetheless, exploiting this technology requires minimization of the implied latency-overhead. This paper offers an exploration of the latest generation of Xilinx all-programmable SoC Zynq devices in terms of their capabilities to reconfigure during run-time. Suitable architectures are provided and performance evaluations are given for both internal configuration interfaces: PCAP and ICAPE2. Moreover, an analysis of the latest tool-chain as well as roadblocks encountered during the progress of this work are presented.

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