FinFET, which is a double-gate field effect transistor (DGFET), is more versatile than traditional single-gate field effect transistors because it has two gates that can be controlled independently. Usually, the second gate of FinFET transistors is used to dynamically control the threshold voltage of the first gate in order to improve the performance and reduce leakage power. However, we can also utilize FinFET's second gate to implement circuits with fewer transistors. This is important since area efficiency is one of the main concerns in circuit design. In this paper, a novel scheme of implementing a majority gate and a 2-1 MUX by using both gates of FinFET transistors as inputs is presented. Simulation results show that FinFET logic implementation has significant advantages over static CMOS logic and pass transistor logic in terms of power consumption and cell area.
[1]
Volkan Kursun,et al.
FinFET domino logic with independent gate keepers
,
2009,
Microelectron. J..
[2]
Luca Benini,et al.
Dynamic Power Management
,
1998
.
[3]
B. Nikolic,et al.
FinFET SRAM with Enhanced Read / Write Margins
,
2006,
2006 IEEE international SOI Conferencee Proceedings.
[4]
Luca Benini,et al.
Decision Diagrams and Pass Transistor Logic Synthesis
,
1997
.
[5]
Anish Muttreja,et al.
CMOS logic design with independent-gate FinFETs
,
2007,
2007 25th International Conference on Computer Design.
[6]
Ching-Te Chuang,et al.
Design and CAD Challenges in sub-90nm CMOS Technologies
,
2003,
ICCAD 2003.