A stereo audio Σ∑ ADC architecture with embedded SNDR self-test

In this paper we present a new architecture for audio analog-to-digital converters (ADCs) that includes a Built-in Self-Test (BIST) technique for the test of the signal-to-noise and distortion ratio (SNDR). A periodical binary stream is generated in the chip in order to stimulate the converter. The reuse of the bandgap circuit already existing in the converter allows us to generate the test stimulus with a very small analog area overhead. The output response analysis is performed by means of a sine-wave fitting algorithm. The reuse of the digital filter already existing in the converter allows us to generate a synchronized reference signal necessary for the fitting algorithm. The BIST technique is equivalent to a standard test carried out with a sinusoidal signal at -12 decibels Full-Scale (dBFS). The total test time is 60 ms and the estimated BIST overhead area is 7.5% of the whole stereo converter area in a 0.13 mum CMOS technology. Experimental results show that the correlation between the embedded self-test and a sinusoidal standard test is excellent, with a SNDR error smaller than 1 dB.

[1]  Matthew Mahoney,et al.  DSP-Based Testing of Analog and Mixed-Signal Circuits , 1987 .

[2]  Degang Chen,et al.  BIST and production testing of ADCs using imprecise stimulus , 2003, TODE.

[3]  Gloria Huertas,et al.  Oscillation-based test in oversampled ΣΔ modulators , 2002 .

[4]  Aubin Roy,et al.  High accuracy stimulus generation for A/D converter BIST , 2002, Proceedings. International Test Conference.

[5]  Guillaume Prenat,et al.  A 0.18 /spl mu/m CMOS implementation of on-chip analogue test signal generation from digital test patterns , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[6]  Florence Azaïs,et al.  Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST , 2001, J. Electron. Test..

[7]  Salvador Mir,et al.  A SNDR BIST for /spl Sigma//spl Delta/ analogue-to-digital converters , 2006, 24th IEEE VLSI Test Symposium.

[8]  Andrea Baschirotto,et al.  Behavioral modeling of switched-capacitor sigma-delta modulators , 2003 .

[9]  Gildas Leger,et al.  Digital Test for the Extraction of Integrator Leakage in 2 nd and 1 st order Σ ∆ Modulators , .

[10]  Adoración Rueda,et al.  Experimental Validation of a Fully Digital BISTfor Cascaded \Sigma \Delta Modulators , 2006, Eleventh IEEE European Test Symposium (ETS'06).

[11]  Gordon W. Roberts,et al.  On-chip analog signal generation for mixed-signal built-in self-test , 1999 .

[12]  Gordon W. Roberts,et al.  A BIST scheme for an SNR test of a sigma-delta ADC , 1993, Proceedings of IEEE International Test Conference - (ITC).

[13]  Kwang-Ting Cheng,et al.  Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysis , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[14]  Gildas Leger,et al.  Digital test for the extraction of integrator leakage in first- and second-order ΣΔ modulators , 2004 .

[15]  Kwang-Ting Cheng,et al.  A new sigma-delta modulator architecture for testing using digital stimulus , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[16]  Chee-Kian Ong,et al.  DfT Sigma-Delta Modulator Architecture Implementation , 2003 .

[17]  Stephen K. Sunter,et al.  A simplified polynomial-fitting algorithm for DAC and ADC BIST , 1997, Proceedings International Test Conference 1997.

[18]  Karim Arabi,et al.  Efficient and accurate testing of analog-to-digital converters using oscillation-test method , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[19]  Jiun-Lang Huang,et al.  Testing second-order delta–sigma modulators using pseudo-random patterns , 2002 .