HAL II: A Mixed Level Hardware Logic Simulation System

This paper describes a mixed level hardware logic simulation system, called Hardware Logic Simulator II (HAL II). This paper first shows a HAL II simulation method. Then, it overviews HAL II hardware and software system configurations, simulation mechanism and estimates system performance. The HAL II system can handle a maximum of 5.8 million gates and a high level design language FDL (Functional Description Language). Finally, it discusses system applications and results. The paper also indicates that HAL II has been successfully used.

[1]  Tom Blank,et al.  A Survey of Hardware Accelerators Used in Computer-Aided Design , 1984, IEEE Design & Test of Computers.

[2]  Nobuhiko Koike,et al.  HAL: A High-Speed Logic Simulation Machine , 1985, IEEE Design & Test of Computers.

[3]  M.M. Denneau The Yorktown Simulation Engine , 1982, 19th Design Automation Conference.

[4]  Nobuhiko Koike,et al.  HAL; A Block Level Hardware Logic Simulator , 1983, 20th Design Automation Conference Proceedings.

[5]  Gregory Francis Pfister,et al.  The Yorktown Simulation Engine: Introduction , 1982, DAC 1982.