THREE-DIMENSIONAL PACKAGING FOR HIGH-PERFORMANCE INTERCONNECT IN LARGE-SCALE VLSI SYSTEMS

The transit time through the interconnect between VLSI components can be a significant fraction of the latency in a large VLSI system. In this paper we describe a scheme for dense, three-dimensional packaging of VLSI components which reduces chip-to-chip transit latencies by reducing interconnect distances. Our packaging scheme sandwiches layers of conventional printed-circuit boards between layers of packaged components to efficiently utilize all three spatial dimensions for interconnect. We introduce the key components of our stack packaging scheme and show how they combine to provide efficient housing for a large range of large-scale VLSI systems.