Koala: a platform for OS-level power management

Managing the power consumption of computing platforms is a complicated problem thanks to a multitude of hardware configuration options and characteristics. Much of the academic research is based on unrealistic assumptions, and has, therefore, seen little practical uptake. We provide an overview of the difficulties facing power management schemes when used in real systems. We present Koala, a platform which uses a pre-characterised model at run-time to predict the performance and energy consumption of a piece of software. An arbitrary policy can then be applied in order to dynamically trade performance and energy consumption. We have implemented this system in a recent Linux kernel, and evaluated it by running a variety of benchmarks on a number of different platforms. Under some conditions, we observe energy savings of 26% for a 1% performance loss.

[1]  Margaret Martonosi,et al.  Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data , 2003, MICRO.

[2]  Rami G. Melhem,et al.  Integrated CPU Cache Power Management in Multiple Clock Domain Processors , 2008, HiPEAC.

[3]  Frank Bellosa,et al.  Process cruise control: event-driven clock scaling for dynamic power management , 2002, CASES '02.

[4]  Lizy Kurian John,et al.  Analysis of dynamic power management on multi-core processors , 2008, ICS '08.

[5]  Norman P. Jouppi,et al.  Single-ISA heterogeneous multi-core architectures for multithreaded workload performance , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[6]  Philip Levis,et al.  Policies for dynamic clock scheduling , 2000, OSDI.

[7]  Gernot Heiser,et al.  An Analysis of Power Consumption in a Smartphone , 2010, USENIX Annual Technical Conference.

[8]  U. Weiser,et al.  Multiple clock and Voltage Domains for chip multi processors , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[9]  Li Shang,et al.  HybDTM: a coordinated hardware-software approach for dynamic thermal management , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[10]  Gu-Yeon Wei,et al.  A fully-integrated 3-level DC/DC converter for nanosecond-scale DVS with fast shunt regulation , 2011, 2011 IEEE International Solid-State Circuits Conference.

[11]  Margaret Martonosi,et al.  An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[12]  Frank Bellosa,et al.  The benefits of event: driven energy accounting in power-sensitive systems , 2000, ACM SIGOPS European Workshop.

[13]  David C. Snowdon,et al.  Accurate on-line prediction of processor and memoryenergy usage under voltage scaling , 2007, EMSOFT '07.

[14]  Scott Shenker,et al.  Scheduling for reduced CPU energy , 1994, OSDI '94.

[15]  Tong Li,et al.  Efficient operating system scheduling for performance-asymmetric multi-core architectures , 2007, Proceedings of the 2007 ACM/IEEE Conference on Supercomputing (SC '07).

[16]  Amin Vahdat,et al.  Currentcy: Unifying Policies for Resource Management , 2002 .

[17]  Paul I. Pénzes,et al.  Energy-delay efficiency of VLSI computations , 2002, GLSVLSI '02.

[18]  Alan Jay Smith,et al.  Improving dynamic voltage scaling algorithms with PACE , 2001, SIGMETRICS '01.

[19]  Michael Gschwind,et al.  New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors , 2003, IBM J. Res. Dev..

[20]  Wu-chun Feng,et al.  Effective Dynamic Voltage Scaling Through CPU-Boundedness Detection , 2004, PACS.

[21]  Lizy Kurian John,et al.  Complete System Power Estimation: A Trickle-Down Approach Based on Performance Events , 2007, 2007 IEEE International Symposium on Performance Analysis of Systems & Software.

[22]  Margaret Martonosi,et al.  Live, Runtime Phase Monitoring and Prediction on Real Systems with Application to Dynamic Power Management , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[23]  R. Kotla,et al.  Characterizing the impact of different memory-intensity levels , 2004, IEEE International Workshop on Workload Characterization, 2004. WWC-7. 2004.

[24]  Frank Bellosa,et al.  Memory-aware Scheduling for Energy Efficiency on Multicore Processors , 2008, HotPower.

[25]  Thomas D. Burd,et al.  Energy efficient CMOS microprocessor design , 1995, Proceedings of the Twenty-Eighth Annual Hawaii International Conference on System Sciences.

[26]  Karthick Rajamani,et al.  IBM Research Report Online Power and Performance Estimation for Dynamic Power Management , 2006 .

[27]  D. Vengerov,et al.  A Methodology for Developing Simple and Robust Power Models Using Performance Monitoring Events , 2009 .

[28]  Norman P. Jouppi,et al.  Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction , 2003, MICRO.

[29]  Christos Kozyrakis,et al.  Full-System Power Analysis and Modeling for Server Environments , 2006 .

[30]  Dave Snowdon OS-level power management , 2010 .

[31]  Amin Vahdat,et al.  ECOSystem: managing energy as a first class operating system resource , 2002, ASPLOS X.

[32]  Saibal Mukhopadhyay,et al.  Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.

[33]  David C. Snowdon,et al.  Power Management and Dynamic Voltage Scaling: Myths and Facts , 2005 .

[34]  Ragunathan Rajkumar,et al.  Critical power slope: understanding the runtime effects of frequency scaling , 2002, ICS '02.

[35]  Philip Levis,et al.  Energy management in mobile devices with the cinder operating system , 2011, EuroSys '11.

[36]  Charles R. Kime,et al.  Logic and Computer Design Fundamentals , 1997 .

[37]  Frank Bellosa,et al.  Energy Management for Hypervisor-Based Virtual Machines , 2007, USENIX Annual Technical Conference.

[38]  Timothy Mattson,et al.  A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[39]  Manuel Prieto,et al.  A comprehensive scheduler for asymmetric multicore systems , 2010, EuroSys '10.

[40]  Massoud Pedram,et al.  Fine-grained dynamic voltage and frequency scaling for precise energy and performance tradeoff based on the ratio of off-chip access to on-chip computation times , 2005 .

[41]  Xi Yang,et al.  Looking back on the language and hardware revolutions: measured power, performance, and scaling , 2011, ASPLOS XVI.

[42]  Luiz André Barroso,et al.  The Case for Energy-Proportional Computing , 2007, Computer.

[43]  Kang G. Shin,et al.  Real-time dynamic voltage scaling for low-power embedded operating systems , 2001, SOSP.

[44]  F.C. Lee,et al.  Analysis of the power delivery path from the 12-V VR to the microprocessor , 2004, IEEE Transactions on Power Electronics.

[45]  Thomas L. Martin,et al.  Balancing batteries, power, and performance: system issues in cpu speed-setting for mobile computing , 1999 .

[46]  Lizy Kurian John,et al.  Runtime identification of microprocessor energy saving opportunities , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[47]  Mahadev Satyanarayanan,et al.  PowerScope: a tool for profiling the energy usage of mobile applications , 1999, Proceedings WMCSA'99. Second IEEE Workshop on Mobile Computing Systems and Applications.

[48]  Sri Parameswaran,et al.  CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time , 2007, 2007 Asia and South Pacific Design Automation Conference.

[49]  Ulrich Kremer,et al.  The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction , 2003, PLDI '03.

[50]  Rajarshi Das,et al.  Coordinating Multiple Autonomic Managers to Achieve Specified Power-Performance Tradeoffs , 2007, Fourth International Conference on Autonomic Computing (ICAC'07).

[51]  James Charles,et al.  Evaluation of the Intel® Core™ i7 Turbo Boost feature , 2009, 2009 IEEE International Symposium on Workload Characterization (IISWC).

[52]  Samuel Naffziger,et al.  An x86-64 core implemented in 32nm SOI CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[53]  C. Pipper,et al.  [''R"--project for statistical computing]. , 2008, Ugeskrift for laeger.

[54]  Ricardo Bianchini,et al.  Energy conservation in heterogeneous server clusters , 2005, PPoPP.

[55]  Carla Schlatter Ellis,et al.  Experiences in managing energy with ECOSystem , 2005, IEEE Pervasive Computing.

[56]  Vibhore Vardhan,et al.  Power Consumption Breakdown on a Modern Laptop , 2004, PACS.