Modeling and comparing CMOS implementations of the C-element

Various applications have demonstrated that asynchronous circuits have great potential for energy-efficient and high-performance design. One of the primitives used in asynchronous control circuits is the C-element. Analytical delay and energy models are presented and applied to the most popular complementary metal-oxide-semiconductor (CMOS) implementations of the C-element. Optimization of these implementations are discussed. The implementations are also compared using simulations. The simulation results are in good agreement with the analytical predictions.

[1]  Ad M. G. Peeters,et al.  Single-rail handshake circuits , 1995, Proceedings Second Working Conference on Asynchronous Design Methodologies.

[2]  Paul Day,et al.  Four-phase micropipeline latch control circuits , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[3]  Wesley A. Clark.  Macromodular computer systems , 1967, AFIPS '67 (Spring).

[4]  Steve Furber.  Computing without Clocks: Micropipelining the ARM Processor , 1995 .

[5]  Kees van Berkel.  Beware the isochronic fork , 1992, Integr..

[6]  Mohamed I. Elmasry,et al.  Optimizing CMOS implementations of the C-element , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[7]  Marly Roncken,et al.  A fully asynchronous low-power error corrector for the DCC player , 1994 .