Modeling Exclusive Memory Access for a Time-Decoupled Parallel SystemC Simulator

The growing complexity of modern embedded systems poses a challenge to designers of virtual platforms, as the increasing number of processors causes simulation speed to degrade. To remain viable as design tools, virtual platforms must use highly abstracted modeling levels or deploy parallel simulation technologies to keep performance up. With multi-core PC workstations being widely available today, parallel simulation seems an attractive solution. However, the introduction of concurrency into a virtual platform simulator complicates the construction of synchronization mechanisms of the simulated models. Therefore, this work presents a modeling approach for concurrent LL/SC based on SystemC/TLM. This facilitated the construction of a parallel simulator for a quad-core OpenRISC based system, gaining a performance speedup of 3.4x over a regular sequential simulator.