Stateful Three-Input Logic with Memristive Switches

Memristive switches are able to act as both storage and computing elements, which make them an excellent candidate for beyond-CMOS computing. In this paper, multi-input memristive switch logic is proposed, which enables the function X OR (Y NOR Z) to be performed in a single-step with three memristive switches. This ORNOR logic gate increases the capabilities of memristive switches, improving the overall system efficiency of a memristive switch-based computing architecture. Additionally, a computing system architecture and clocking scheme are proposed to further utilize memristive switching for computation. The system architecture is based on a design where multiple computational function blocks are interconnected and controlled by a master clock that synchronizes system data processing and transfer. The clocking steps to perform a full adder with the ORNOR gate are presented along with simulation results using a physics-based model. The full adder function block is integrated into the system architecture to realize a 64-bit full adder, which is also demonstrated through simulation.

[1]  H. Fröhlich.  Electronic Processes in Ionic Crystals , 1949, Nature.

[2]  William H. Kautz,et al.  Cellular Logic-in-Memory Arrays , 1969, IEEE Transactions on Computers.

[3]  Yuan Taur,et al.  Device scaling limits of Si MOSFETs and their application dependencies , 2001, Proc. IEEE.

[4]  G. Snider,et al.  Computing with hysteretic resistor crossbars , 2005 .

[5]  A. Nordström,et al.  What's next for WHO? , 2006, The Lancet.

[6]  S. Sze,et al.  Physics of Semiconductor Devices: Sze/Physics , 2006 .

[7]  Yu Cao,et al.  New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration , 2006, IEEE Transactions on Electron Devices.

[8]  R. Waser,et al.  Nanoionics-based resistive switching memories. , 2007, Nature materials.

[9]  H. Ohno,et al.  Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions , 2008 .

[10]  J. Yang,et al.  Memristive switching mechanism for metal/oxide/metal nanodevices. , 2008, Nature nanotechnology.

[11]  Mika Laiho,et al.  Stateful implication logic with memristors , 2009, 2009 IEEE/ACM International Symposium on Nanoscale Architectures.

[12]  R. Dittmann,et al.  Redox‐Based Resistive Switching Memories – Nanoionic Mechanisms, Prospects, and Challenges , 2009, Advanced materials.

[13]  Gregory S. Snider,et al.  ‘Memristive’ switches enable ‘stateful’ logic operations via material implication , 2010, Nature.

[14]  Sung-Mo Kang,et al.  Field Programmable Stateful Logic Array , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  R Rosezin,et al.  Crossbar Logic Using Bipolar and Complementary Resistive Switches , 2011, IEEE Electron Device Letters.

[16]  R. Dittmann,et al.  Origin of the Ultra‐nonlinear Switching Kinetics in Oxide‐Based Resistive Switches , 2011 .

[17]  Sung-Mo Kang,et al.  Reconfigurable Stateful nor Gate for Large-Scale Logic-Array Integrations , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[18]  Peter J. Roberts,et al.  Accessed from , 2022 .

[19]  U. Böttger,et al.  Beyond von Neumann—logic operations in passive crossbar arrays alongside memory operations , 2012, Nanotechnology.

[20]  Sung-Mo Kang,et al.  Memristive XOR for resistive multiplier , 2012 .

[21]  G. C. Sirakoulis,et al.  A Novel Design and Modeling Paradigm for Memristor-Based Crossbar Circuits , 2012, IEEE Transactions on Nanotechnology.

[22]  S. Kvatinsky,et al.  MRL — Memristor Ratioed Logic , 2012, 2012 13th International Workshop on Cellular Nanoscale Networks and their Applications.

[23]  Xuejun Yang,et al.  Performing Stateful Logic on Memristor Memory , 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

[24]  J Joshua Yang,et al.  Memristive devices for computing. , 2013, Nature nanotechnology.

[25]  Uri C. Weiser,et al.  Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[26]  Anne Siemon,et al.  Applicability of Well-Established Memristive Models for Simulations of Resistive Switching Devices , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[27]  Eike Linn,et al.  Memristive nano-crossbar arrays enabling novel computing paradigms , 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

[28]  Stephan Menzel,et al.  Simulation and comparison of two sequential logic-in-memory approaches using a dynamic electrochemical metallization cell model , 2014, Microelectron. J..

[29]  Uri C. Weiser,et al.  MAGIC—Memristor-Aided Logic , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[30]  Anupam Chattopadhyay,et al.  In-memory adder functionality in 1S1R arrays , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

[31]  Anne Siemon,et al.  A Complementary Resistive Switch-Based Crossbar Array Adder , 2015, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[32]  S. Menzel,et al.  Physics of the Switching Kinetics in Resistive Memories , 2015 .

[33]  Said Hamdioui,et al.  Fast boolean logic mapped on memristor crossbar , 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).

[34]  Mayler G. A. Martins,et al.  Factored Forms for Memristive Material Implication Stateful Logic , 2015, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[35]  H-S Philip Wong,et al.  Memory leads the way to better computing. , 2015, Nature nanotechnology.

[36]  S. Menzel,et al.  A HfO2‐Based Complementary Switching Crossbar Adder , 2015 .

[37]  Stefano Ambrogio,et al.  Normally-off Logic Based on Resistive Switches—Part II: Logic Circuits , 2015, IEEE Transactions on Electron Devices.

[38]  Nishil Talati,et al.  Logic Design Within Memristive Memories Using Memristor-Aided loGIC (MAGIC) , 2016, IEEE Transactions on Nanotechnology.

[39]  S. Menzel,et al.  Uniting Gradual and Abrupt set Processes in Resistive Switching Oxides , 2016 .

[40]  Giovanni De Micheli,et al.  The Programmable Logic-in-Memory (PLiM) computer , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[41]  Brian D. Hoskins,et al.  Optimized stateful material implication logic for three-dimensional data manipulation , 2016, Nano Research.

[42]  S. Menzel,et al.  Ultrafast switching in Ta2O5-based resistive memories , 2016, 2016 IEEE Silicon Nanoelectronics Workshop (SNW).

[43]  Giovanni De Micheli,et al.  The Programmable Logic-in-Memory (PLiM) Computer (Invited) , 2016, DATE 2016.

[44]  Nima Taherinejad,et al.  An improved algorithm for IMPLY logic based memristive Full-adder , 2017, 2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE).

[45]  Junhwan Choi,et al.  Zero-static-power nonvolatile logic-in-memory circuits for flexible electronics , 2017, Nano Research.

[46]  Heiner Giefers,et al.  Mixed-precision in-memory computing , 2017, Nature Electronics.

[47]  Yi Li,et al.  Reprogrammable logic in memristive crossbar for in-memory computing , 2017 .

[48]  R. Stanley Williams.  What's Next? , 2017, Computing in Science & Engineering.

[49]  Wei Lu,et al.  The future of electronics based on memristive systems , 2018, Nature Electronics.

[50]  Javier Martin-Martinez,et al.  Experimental Time Evolution Study of the HfO2-Based IMPLY Gate Operation , 2018, IEEE Transactions on Electron Devices.

[51]  H.-S. Philip Wong,et al.  In-memory computing with resistive switching devices , 2018, Nature Electronics.

[52]  Ronald Tetzlaff,et al.  Requirements and Challenges for Modelling Redox-based Memristive Devices , 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

[53]  Paolo Pavan,et al.  Energy-Efficient Logic-in-Memory I-bit Full Adder Enabled by a Physics-Based RRAM Compact Model , 2018, 2018 48th European Solid-State Device Research Conference (ESSDERC).

[54]  Joseph S. Friedman,et al.  Overhead Requirements for Stateful Memristor Logic , 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

[55]  Said Hamdioui,et al.  Memristive Device Modeling and Circuit Design Exploration for Computation-in-Memory , 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

[56]  Alessandro Freddi,et al.  Design Principles and Methodologies , 2018, Springer Tracts in Mechanical Engineering.

[57]  Robert Keller.  Logic Circuits , 2020, Semiconductor Basics.